1. Field of the Invention
This invention relates to integrated circuits.
2. Description of the Prior Art
Some data processing integrated circuits comprise a number of data handling devices such as a microprocessor, random access memory (RAM), data buffers or other peripheral logic functions, fabricated as a single semiconductor chip. These on-chip data handling devices (referred to `internal` data handling devices) are interconnected to allow data communication between the devices, for example by means of a common data bus.
During data communication between internal data handling devices, the communicating devices can be controlled by a clocking pulses of a common clock signal. The communicating devices can operate synchronously in this way because the physical proximity of the devices means that any propagation delays for data transfer between the devices are negligible.
The clocking of data communication between an internal data handling device and an external (off-chip) data handling device, such as an external RAM device, is not so straightforward. Generally, data buffering is required in order to interface between internal and external devices. In particular, data transferred from an internal device to an external device is buffered by an output data buffer, and data transferred from an external device to an internal device is buffered by an input data buffer. Both of these data buffers introduce propagation delays, which can depend on a number of factors such as the basic operation speed of the integrated circuit, temperature, operating voltage and the capacitative loading of the data buffers.
The propagation delays introduced by the data buffers mean that data signals generated by an internal data handling device are received by an external device slightly late, with respect to the clocking of the internal devices, and data signals returned by the external device are received later still by the internal devices. This means that data signal returned by an external device are not synchronised with the clocking of the internal devices.
One previously proposed solution to this problem is to employ so-called wait states, whereby on-chip processing is suspended for one or more clock cycles to allow data signals received from external data handling devices to be re-synchronised with the clocking of the internal devices. However, the use of wait states slows down the overall operation of the integrated circuit, especially in applications requiring frequent accessing of external data handling devices.
A further requirement imposed on many integrated circuits is that of a low power consumption. This is particularly the case for integrated circuits intended for use in battery-powered portable equipment. This requirement means that another possible solution to the above problems, namely the use of faster data buffers and external devices, is undesirable, since the power consumption of such devices increases with their processing speed.